Self-Aligned Internal Spacer With EUV

ABSTRACT

A method of forming aligned gates for horizontal nanowires or nanosheets, comprising: providing a wafer which comprises at least one fin of sacrificial layers alternated with functional layers, and a dummy gate covering a section of the fin between a first end and a second end; at least partly removing the sacrificial layers at the first end and the second end thereby forming a void between the functional layers at the first and end such that the void is partly covered by the dummy gate; providing resist material which oxidizes upon EUV exposure; exposing the wafer to EUV light; selectively removing the dummy gate and the unexposed resist; forming a gate between the functional layers and between the exposed resist at the first end and at the second end.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a non-provisional patent application claimingpriority to European Patent Application No. 18171948.5, filed on May 11,2018, the contents of which are hereby incorporated by reference.

FIELD OF THE DISCLOSURE

The disclosure relates to the field of semiconductor devices comprisingnanowires or nanosheets. More specifically it relates to a method offorming a semiconductor device comprising nanowires or nanosheets.

BACKGROUND

Stacked nanowires built from a Si/SiGe superlattice are one of the maincontenders for the 7 nm node architecture, as the wrapped around gateoffers ultimate control of the channel.

The complexity of this architecture stems from the need to integrate thegate between the channels. An internal spacer must be included toseparate the junctions from the buried gates, otherwise the parasiticcapacitance of the transistors damage excessively the electricalperformance. In the standard flow the internal spacers (defining theburied gate length) are processed by a wet etch of the sacrificial SiGe.After the recess of the sacrificial SiGe the internal spacer is insertedfrom the sides (see for example U.S. Pat. No. 9,484,447 B2).

This creates an additional problem of gate length variation in thenanowire stack, because the buried gate length is defined by the spacerrecess and is therefore not self-aligned with the top gate. Therefore,gate length variation may arise between the different nanowires stakedtogether.

To solve this issue, a “nanowire-first” flow using e-beam and HSQlithography was explored. It exploits the ability of e-beam lithographyto expose HSQ through the stacked channels and was explored by CEA-LETIand is explained in “Innovative through-Si 3D lithography for ultimateSelf-Aligned Planar Double-Gate and Gate-All-Around nanowiretransistors” Coquand VLSI 2013. The nanowires are released before thedummy gate formation, in contrast to the standard flow (e.g. U.S. Pat.No. 9,484,447 B2) where the SiGe is released after dummy gate removal.This flow is difficult to apply in an industrial environment due to thelow throughput of the e-beam process, and the pillars on the sides ofthe channel which are used to maintain the released nanowire withoutsupporting gates.

In view of these problems there is room for improvement in methods offorming a semiconductor device comprising nanowires or nanosheets.

SUMMARY

The present disclosure provides a method of forming a semiconductordevice comprising nanowires or nanosheets.

Embodiments of the present disclosure relate to a method of formingaligned gates for horizontal nanowires or nanosheets. These methodscomprise the following steps.

Providing a wafer. The wafer comprises a semiconductor structure whichcomprises at least one fin. The at least one fin comprises a stack ofsacrificial layers alternated with functional layers. The semiconductorstructure comprises a dummy gate which covers a section of the finbetween a first end of the section and a second end of the section.

At least partly removing the sacrificial layers in between thefunctional layers, at the first end and the second end of the section.Thereby a void is formed between the functional layers at the first endof the section and a void is formed between the functional layers at thesecond end of the section. The void at the first end is partly coveredby the dummy gate, and part is not covered by the dummy gate. The voidat the second end is partly covered by the dummy gate, and part is notcovered by the dummy gate.

Providing resist material in the void at the first end of the sectionand in the void at the second end of the section. The resist material isselected such that it oxidizes upon EUV exposure.

Exposing the wafer to EUV light thereby converting the exposed resist toan oxide. Only the resist which is not covered by the dummy gate will beexposed. The resist under the dummy gate is unexposed.

Selectively removing the dummy gate and the unexposed resist.

Forming a gate between the functional layers and between the exposedresist at the first end and the exposed resist at the second end of thesection. Thus, gates are obtained which are aligned with the exposedresist at the first end and the second end of the section. These gatesare gates for the functional layers. The functional layers are therebycorresponding with the nanowires or nanosheets.

By using an EUV/resist lithography, a self-aligned internal spacer canbe obtained in vertically stacked nanowires or nanosheets. Using thedummy gate as an EUV mask, the resist is only exposed outside the gate,and densifies into an oxide at the exposed locations. This oxide formsthe self-aligned internal spacer. This solves the issue of gate lengthvariations between the different channels of the stack.

Some of embodiments of the present disclosure allow for a highthroughput to be obtained thanks to EUV.

In embodiments of the present disclosure the provided resist material ishydrogen silsesquioxane.

In some embodiments of the present disclosure, HSQ converts into SiO_(x)after exposing it to EUV light (x may for example be between 1 and 2).This allows for the removal of the unexposed HSQ while keeping theSiO_(x) in place.

In embodiments of the present disclosure, the resist is applied by spincoating.

In embodiments of the present disclosure, the sacrificial layer ispartly removed such that a pillar of the sacrificial layer is remaining.A width of this pillar is shorter than a predefined gate length. Thepredefined gate length thereby corresponds to the gate length defined bythe dummy gate. This is the length between the first end and the secondend of the section of the fin.

Some embodiments of the present disclosure remove the need to have padson each side of the transistor since the supporting pillar is supportingthe functional layers.

In embodiments of the present disclosure forming the gate comprises: (i)depositing gate dielectric material around the nanowires or nanosheets,and (ii) depositing gate material around the gate dielectric materialthereby forming the gate.

In embodiments of the present disclosure, the sacrificial layers are atleast partly removed by isotropic etching.

In embodiments of the present disclosure, a source is formed at one sideof the nanowire material next to the dummy gate or gate and a drain isformed at an opposite end of the nanowire material at the opposite sideof the dummy gate or gate.

In embodiments of the present disclosure, an implant anneal step isapplied. It may be beneficial when that anneal step is applied afterremoving the unexposed resist. Heating before removal of the unexposedresist would result in an oxidation of the resist and hence to a lessaccurately defined gate length.

In embodiments of the present disclosure, providing the wafer comprisesdepositing a stack of layers on a substrate. The stack of layerscomprises alternating sacrificial and functional layers. Afterdepositing the stack at least one fin is formed in the stack.

In embodiments of the present disclosure, at least two functional layersare deposited or even at least three functional layers are deposited.

In embodiments of the present disclosure, depositing of the stackcomprises depositing functional layers which are comprising Silicon, orSiGe, or Ge, or InGaAs, or III-V material.

Some embodiments of the present disclosure allow for them to be appliedto different nanowire or nanosheet device architectures. Examplesinclude are Si, SiGe, Ge, or III/V nanowire/nanosheet integrationschemes. Other example may be possible.

In embodiments of the present disclosure, depositing of the stackcomprises depositing functional layers which are comprising Ge andsacrificial layers which are comprising SiGe.

In embodiments of the present disclosure, depositing of the stackcomprises depositing functional layers which are comprising Si andsacrificial layers which are comprising SiGe.

Some aspects of the disclosure are set out in the accompanyingindependent and dependent claims. Features from the dependent claims maybe combined with features of the independent claims and with features ofother dependent claims as appropriate and not merely as explicitly setout in the claims.

These and other aspects of the disclosure will be apparent from andelucidated with reference to the embodiment(s) described hereinafter.

BRIEF DESCRIPTION OF THE FIGURES

The above, as well as additional, features will be better understoodthrough the following illustrative and non-limiting detailed descriptionof example embodiments, with reference to the appended drawings.

FIG. 1 shows a cross-section in the length direction of a fin of asemiconductor structure, according to an example embodiment.

FIG. 2 schematically shows a cross-section orthogonal to the lengthdirection of the fin of FIG. 1, wherein the channel is covered by thedummy gate.

FIG. 3 schematically shows a cross-section of the resulting stack afterpartly removing the sacrificial layer, according to an exampleembodiment.

FIG. 4 schematically shows a cross-section of the resulting stack afterresist deposition and etching, according to an example embodiment.

FIG. 5 shows the stack after exposure to EUV, according to an exampleembodiment.

FIG. 6 shows the stack after applying an external spacer over the dummygate, according to an example embodiment.

FIG. 7 shows the stack after recessing the internal spacer, according toan example embodiment.

FIG. 8 shows a cross-section of stacked gates without diffusion breakafter recessing the internal spacer, according to an example embodiment.

FIG. 9 shows the stack after epitaxially growing source/drain materialin the voids between the nanowires or nanosheets, according to anexample embodiment.

FIG. 10 shows a schematic drawing of the stack after ILD filling andselectively removing the dummy gate, according to an example embodiment.

FIG. 11 shows a schematic drawing of the stack after removal of thesacrificial material through the gate, according to an exampleembodiment.

FIG. 12 shows a schematic drawing of the stack after removal of theunexposed resist through the gate, according to an example embodiment.

FIG. 13 shows a schematic drawing of the stack after forming ahigh-K/metal gate, according to an example embodiment.

FIG. 14 schematically shows a cross-section orthogonal to the lengthdirection of the fin of FIG. 13.

FIG. 15 shows different steps of a method, according to an exampleembodiment.

All the figures are schematic, not necessarily to scale, and generallyonly show parts which are necessary to elucidate example embodiments,wherein other parts may be omitted or merely suggested.

DETAILED DESCRIPTION

Example embodiments will now be described more fully hereinafter withreference to the accompanying drawings. That which is encompassed by theclaims may, however, be embodied in many different forms and should notbe construed as limited to the embodiments set forth herein; rather,these embodiments are provided by way of example. Furthermore, likenumbers refer to the same or similar elements or components throughout.

The present disclosure will be described with respect to particularembodiments and with reference to certain drawings but the disclosure isnot limited thereto but only by the claims. The drawings described areonly schematic and are non-limiting. In the drawings, the size of someof the elements may be exaggerated and not drawn on scale forillustrative purposes. The dimensions and the relative dimensions do notcorrespond to actual reductions to practice of the disclosure.

Moreover, the terms top, under and the like in the description and theclaims are used for descriptive purposes and not necessarily fordescribing relative positions. It is to be understood that the terms soused are interchangeable under appropriate circumstances and that theembodiments of the disclosure described herein are capable of operationin other orientations than described or illustrated herein.

It is to be noticed that the term “comprising”, used in the claims,should not be interpreted as being restricted to the means listedthereafter; it does not exclude other elements or steps. It is thus tobe interpreted as specifying the presence of the stated features,integers, steps or components as referred to, but does not preclude thepresence or addition of one or more other features, integers, steps orcomponents, or groups thereof. Thus, the scope of the expression “adevice comprising means A and B” should not be limited to devicesconsisting only of components A and B. It means that with respect to thepresent disclosure, the only relevant components of the device are A andB.

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure or characteristicdescribed in connection with the embodiment is included in at least oneembodiment of the present disclosure. Thus, appearances of the phrases“in one embodiment” or “in an embodiment” in various places throughoutthis specification are not necessarily all referring to the sameembodiment, but may. Furthermore, the particular features, structures orcharacteristics may be combined in any suitable manner, as would beapparent to one of ordinary skill in the art from this disclosure, inone or more embodiments.

Similarly, it should be appreciated that in the description of exampleembodiments of the disclosure, various features of the disclosure aresometimes grouped together in a single embodiment, figure, ordescription thereof for the purpose of streamlining the disclosure andaiding in the understanding of one or more of the various aspects. Thismethod of disclosure, however, is not to be interpreted as reflecting anintention that the claims require more features than are expresslyrecited in each claim. Rather, as the following claims reflect, someaspects lie in less than all features of a single foregoing disclosedembodiment. Thus, the claims following the detailed description arehereby expressly incorporated into this detailed description, with eachclaim standing on its own as a separate embodiment of this disclosure.

Furthermore, while some embodiments described herein include some butnot other features included in other embodiments, combinations offeatures of different embodiments are meant to be within the scope ofthe disclosure, and form different embodiments, as would be understoodby those in the art. For example, in the following claims, any of theclaimed embodiments can be used in any combination.

In the description provided herein, numerous specific details are setforth. However, it is understood that embodiments of the disclosure maybe practiced without these specific details. In other instances,well-known methods, structures and techniques have not been shown indetail in order not to obscure an understanding of this description.

Where in embodiments of the present disclosure reference is made tonanowire material or nanosheet material, reference is made to materialfrom which the functional layers, and hence the resulting nanowires ornanosheets are made.

Where in embodiments of the present disclosure reference is made tosacrificial material, reference is made to material from which thesacrificial layers are made.

Embodiments of the present disclosure relate to a method for formingaligned gates for nanowires or nanosheets. The disclosure reported hereuses self-aligned resist-based internal spacers. A fin comprising astack of sacrificial layers alternated with functions layers is partlycovered by a dummy gate. The side-recess of the sacrificial layer ispushed further under the dummy gate, and the resulting gap is filled byresist. Using EUV (extreme ultraviolet) lithography, the resist belowthe gate is not exposed and can be removed selectively later. The resistis selected such that the exposed resist turns into an oxide which canbe used as an internal spacer. The boundary between the non-exposedresist and oxide later defines the gate length of the stacked nanowiresor nanosheets during the dummy gate removal. This process also solvesthe throughput issue since EUV can be used to expose the resist in aself-aligned way, in contrast to a flow where the e-beam defines eachgate individually.

In embodiments of the present disclosure, the dummy gate is used for theself-aligned step. As a result, the internal edge of the spacer isself-aligned. This may be beneficial because the internal edge of thespacer defines the gate length. The present disclosure enables the samegate length between all the nanowires or nanosheets of the stack. Thereis, moreover, no opacity requirement for the spacer, since the externalspacer is not used as a mask.

A method 100 according to embodiments of the present disclosurecomprises the following steps (also illustrated in FIG. 13).

Providing 110 a wafer comprising a semiconductor structure whichcomprises at least one fin. The at least one fin comprises a stack ofsacrificial layers 4 alternated with functional layers 3. Thesemiconductor structure comprises a dummy gate 1 which partly covers thestack of layers of the at least one fin. The dummy gate may for examplecover the top of the fin and the sidewalls of the fin over a section ofthe fin. Such a section extends over part of the length of the finbetween a first end 21 and a second end 22 of the section.

The method also comprises at least partly removing 120 the sacrificiallayers 4 in between the functional layers 3, under the dummy gate 1thereby forming a void between the functional layers under the dummygate 1. Thus, a void (i.e. empty space) which can be filled with resistmaterial is created at both ends of the section. A void is present atthe first end 21 and at the second end 22 of the section. The void atthe first end 21 is on one side of the first end covered by the dummygate and at the other side of the first end not covered by the dummygate. The is similar for the void at the second end 22. The void at thefirst end 21 of the section may extend to the void at the second end 22of the section. In some embodiments of the present disclosuresacrificial material may be remaining underneath the dummy gate. In someembodiments of the present disclosure it may be completely removed.

Resist material is provided 130 within the void at the first end and atthe second end of the section. The resist material is selected such thatit oxidizes upon EUV exposure.

In a next step the wafer is exposed to EUV light such that the part ofthe resist which is covered by the dummy gate is not exposed to the EUVlight. The part of the resist that is exposed to the EUV light isconverted to an oxide.

In a next step the dummy gate and the unexposed resist are selectivelyremoved 150.

In a next step a gate is formed 160 around the released nanowires ornanosheets (at the former position of the unexposed resist and thesacrificial material underneath the dummy gate). This gate is presentbetween the functional layers and between the exposed resist at thefirst side and the second side of the section. The exposed resist (i.e.the oxidized resist) thereby delineates the gate. Thus, gates areobtained which are aligned with the edges of the oxidized resist. Theseedges are defined by the EUV which did not reach the resist which wascovered by the dummy gate. The functional layers are corresponding withthe nanowires or nanosheets.

The difference between a nanowire and a nanosheet is in the ratiobetween the width and the height of the nanowire or the nanosheet. For ananowire this ratio may be around one whereas for a nanosheet it islarger than one (a typical ratio could for example be between 3 and 20).A nanowire may for example have a width of around 7 nm. The disclosureis, however, not limited thereto.

Using this method nanowires or nanosheets may be obtained with a gateall around the nanowire or nanosheet. The gate length is defined by theexposure of the resist by the EUV.

The resist material may be a resin. It may for example be hydrogensilsesquioxane (HSQ).

In e-beam and EUV, the exposure of the resist is induced by secondaryelectrons emitted by the photons (EUV) or by primary electrons (e-beam).

Secondary electrons can be generated through the stack of functional andsacrificial layers (this may for example be a stack of Si and SiGelayers). Exposure through the functional layers (e.g. Si) is possible inboth cases.

EUV allows full wafer exposure. This is not possible with e-beam. EUV,moreover, allows self-aligned patterning. This is also not possible withe-beam as the electron energy is too high for self-aligned patterning ine-beam. This is due to the penetration of the primary electrons of thee-beam which is not stopped by the gate, while the penetration of theEUV photons in the hard mask is preventing them from reaching thechannel.

If the penetration depth of the secondary electrons does not createenough contrast, a layer which is attenuating or even blocking EUV canbe added in the gate stack. This may be beneficial to reduce the flux ofthe EUV towards the channel. This is, however, not strictly necessarywhen the hard mask in the gate stack is reducing the flux of the EUVsufficiently such that only a limited amount is reaching the channelbelow the gate.

FIG. 1 to FIG. 12 show cross-sections of a semiconductor structurecomprising a fin. Each cross-section is parallel to the longitudinaldirection of the fin and orthogonal to the wafer. The different figuresshow different intermediate stacks for different steps in the method, inaccordance with embodiments of the present disclosure. In these figuresthe sacrificial layers are SiGe layers and the functional layers as Silayers. The disclosure is however not limited to these materials. Inembodiments of the present disclosure, the sacrificial layers may beSiGe layers and the functional layers may be Si layers. In embodimentsof the present disclosure, the functional layers may for examplecomprise Silicon, or SiGe, or Ge, or InGaAs, or III-V material.

FIG. 1 shows a semiconductor structure which is provided 110 in a methodaccording to an example embodiment. FIG. 1 shows a cross-section in thelength direction of a fin of the semiconductor structure. FIG. 2schematically shows a cross-section of the same semiconductor structureorthogonal to the length direction of the fin.

For obtaining this stack, a silicon wafer (e.g. (100)) 2 is provided. Inthis wafer well implantations may be provided. Next a superlattice isprovided comprising Si layers 3, and SiGe layers 4. This stack ofsuperlayers may be obtained using epitaxial growth.

The thickness of the Si layers may for example be between 2 nm and 20nm. The thickness of the SiGe layers may for example be between 2 nm and20 nm. The numbers of Si layers or SiGe layers may for example bebetween 2 and 10.

After providing the alternating stack of functional and sacrificiallayer, fins are fabricated. These may be fabricated usingself-aligned-double-patterning.

Shallow trench isolations 0 (STI) may be provided by STI etching,followed by STI fill and recess.

A buffer oxide, also known as PAD oxide may be applied on top of thefins. This PAD oxide may be considered to be part of the dummy gate. Thedummy gate may for example comprise an oxide layer, a polysilicon layer,and a hard mask. The hardmask may for example comprise SiO₂ and SiN.

A dummy gate 1 is applied on top of the fins (e.g. on top of the bufferoxide). The dummy gate covers a section of the fin between a first end21 and a second end 22 of the section.

These ends are illustrated by the dashed lines in FIG. 1 (and in some ofthe following drawings, but not in all in order not to overload them).The dummy gate may for example be a dummy polysilicon gate. Afterproviding the dummy gate 1, a SiO₂ hardmask may be applied on the dummygate. This step may be followed by a step wherein the SiO₂ hardmask ispatterned, and after which the dummy gate is patterned. This step may befollowed by extension implantations.

FIG. 3 schematically shows a cross-section of the resulting stack afterpartly removing the sacrificial layers 4. After recessing thesacrificial layers (SiGe recess) the nanowire or nanosheet 3 is partlyreleased. Optionally a pillar 4 of sacrificial material (e.g. SiGe) mayremain at the center, after removing the sacrificial material from bothsides of the dummy gate. These remaining pillars 4 may serve to supportthe nanowires to avoid that the nanowires or nanosheets collapse.Instead of, or in combination with the pillars the dummy gate 1 maysupport the nanowires or nanosheets. Some embodiments of the presentdisclosure remove the need for supporting pads. In embodiments of thepresent disclosure the sacrificial layers may be completely removed.

Although in FIG. 3 and FIG. 4 the remaining parts of the sacrificiallayer 4 are drawn as if they are aligned with each other, this is notrequired. A non-aligned removal (e.g. by etching) of the sacrificiallayer is allowable if the remaining pillars (if any) are within thelongitudinal spacing of the eventual gate.

After removing the sacrificial material, the resulting voids are filledwith resist material. This material is selected such that it oxidizesupon EUV exposure (the resist may for example comprise HSQ). FIG. 4shows the resist 5 after resist deposition and etching. The resist mayfor example be deposited by spin coating. The deposition step may befollowed by dry etching. Where HSQ is used as resist, the HSQconformality allow for the filling of narrow spaces between two stackedfunctional layers.

After providing 130 the resist within the void, the full wafer isexposed to EUV light. The exposed resist will thereby convert into anoxide 6. FIG. 5 shows the stack after exposure to EUV. The part of theresist (e.g. HSQ) which is exposed to the EUV is converted into an oxide6 (e.g. Si_(x)). This is the internal spacer. HSQ will for exampleconvert into SiO_(x). The resist under the dummy gate which is notexposed to the EUV light is not converted. The edge between theconverted resist (e.g. SiO_(x)) and the unconverted resist (e.g. HSQ) isaligned on the dummy gate.

FIG. 6 shows the stack after applying an external spacer 7 over thedummy gate. A SiN spacer may for example be deposited and etched suchthat the internal spacer (the exposed resist) is accessible for etching.

FIG. 7 and FIG. 8 show a stack after recessing the internal spacer 6.

Next the source/drain 10 may be deposited. This may be achieved byepitaxially growing the source/drain material (e.g. silicon) in thevoids between the nanowires or nanosheets. The epitaxial growth is doneat low temperature. The reason therefore is that under the gateunconverted resist (e.g. HSQ) is present. As long as the length of thegates is not yet fixed, the temperature of the following processingsteps should not too high to prevent unconverted resist to convert intoan oxide because this would result in a change of the gate length.

Solid phase epitaxial regrowth (SPER) may for example be applied. Thetemperature is below the temperature at which the resist would oxidize.Thus, oxidation of the not exposed resist is prevented. Instead ofepitaxially growing the material an amorphous material may be deposited.FIG. 9 illustrates the resulting stack after epitaxially growingsilicon. This step may be followed by an implant step.

An interlayer dielectric (ILD) may be deposited over the stack and overthe SiN spacer, followed by ILD chemical mechanical polishing (CMP) onthe gate.

FIG. 10 shows a schematic drawing of the stack after ILD (interlayerdielectric) filling and after selectively removing the dummy gate. Inthis graph the layer 11 represents the ILD.

FIG. 11 shows a schematic drawing of the stack after removal of thesacrificial material 4 (e.g. SiGe) through the gate.

FIG. 12 shows a schematic drawing of the stack after removal of theunexposed resist 5 (e.g. unexposed HSQ) through the gate.

After removal of the unexposed HSQ high temperature steps may beperformed such as a heavily doped drain (HDD) anneal step and a SPERcrystallization step.

In methods according to embodiments of the present disclosure, a gate isformed around the released nanowires or nanosheets (at the formerposition of the unexposed resist and the sacrificial material underneaththe dummy gate). A high-K/metal gate may be deposited (high K+ workfunction metal deposition). The gate dielectric layer may be obtained byatomic layer deposition of HfO₂. The gate materials may be workfunctionmetals, such as TiN, TiC, TaN or TiAl. W filling may be done for thecontacting.

An example of a resulting stack is schematically illustrated in FIG. 13and FIG. 14 showing a gate oxide 8 and a gate metal 9 (replacementgate). FIG. 13 shows a cross-section in the length direction of the finwhereas FIG. 14 shows a cross-section orthogonal to the length directionof the fin. Planarization may be achieved using CMP.

In embodiments of the present disclosure, the resulting gate may forexample have a length between 7 nm and 200 nm, for example of 20 nm. Theaccuracy of the gate length may for example range between 0 and 3 nm.

Due to its high energy, EUV radiation is absorbed in practically allmaterials. However, the emission wavelength of EUV lithography (e.g.between 11 and 14 nm, e.g. about 13.5 nm) corresponds to a peak of thepenetration depth for Silicon (900 nm). Therefore, EUV lithographythrough Si is possible. Also, SiGe and III-V materials have a sufficientpenetration depth for the principle of this disclosure to work.

The EUV photons penetration is much lower in the hard mask of the dummygate (about 100 nm which is close to 10 times less). Therefore, thedummy gate is efficient as an EUV mask. The disclosure is applicable tostacks wherein the penetration length of the dummy gate is shorter thanthe penetration length through the functional layers. In that case thedifference in penetration length allows to obtain a self-alignedinternal spacer. Fine-tuning of the dummy gate allows to maximize thecontrast. This can be achieved by tuning the hard mask thickness and thecomposition (e.g. by adding oxides which are opaque to EUV)

In embodiments of the present disclosure, the applied resist may be HSQ.To avoid that the thermal budget causes the HSQ resist to transform intoSiO₂ the unexposed HSQ is preferably not exposed to temperatures above400° C. As already explained when elaborating on the method steps in theprevious paragraphs the high temperatures may for example be avoided bya very low temperature EPI or by a delayed thermal step (using e.gSPER). The high temperature step can for example be shifted between thestep wherein the sacrificial material and the unexposed resist areremoved (e.g. HSQ/SiGe removal) and the step wherein the gate isdeposited (e.g. HKMG deposition). This will cause nanowire or nanosheettrimming due to oxidation but this is acceptable.

In embodiments of the present disclosure wherein HSQ is used as resistand wherein the HSQ is exposed to EUV, a resolution down to 20 nm oreven smaller is achievable.

The process flow is also effective between gates without active break.FIG. 8 shows a cross-section of stacked gates without diffusion break.In that case the sacrificial material is removed between the two gatesand the nanosheets or nanowires extend between the two gates.

The following steps may be applied:

a) dummy gate patterning

b) recess of the sacrificial material (e.g. SiGe)

c) filling of the resist (e.g. HSQ)+dry etch+expose to EUV

d) recess of the resist.

Using embodiments of the present disclosure it is possible to createvertically stacked gate all around devices. Nanowires or nanosheets witha gate all around the nanowire or nanosheet can be obtained.

Methods according to embodiments of the present disclosure may, forexample, be deployed in a CMOS 7 nm process flow.

While some embodiments have been illustrated and described in detail inthe appended drawings and the foregoing description, such illustrationand description are to be considered illustrative and not restrictive.Other variations to the disclosed embodiments can be understood andeffected in practicing the claims, from a study of the drawings, thedisclosure, and the appended claims. The mere fact that certain measuresor features are recited in mutually different dependent claims does notindicate that a combination of these measures or features cannot beused. Any reference signs in the claims should not be construed aslimiting the scope.

What is claimed is:
 1. A method of forming aligned gates for horizontalnanowires or nanosheets, the method comprising: providing a wafercomprising a semiconductor structure which comprises at least one fin,the at least one fin comprising a stack of sacrificial layers alternatedwith functional layers, the semiconductor structure comprising a dummygate covering a section of the fin between a first end of the sectionand a second end of the section, at least partly removing the stack ofsacrificial layers in between the functional layers, at the first endand the second end of the section thereby forming a void between thefunctional layers at the first end of the section and a void at thesecond end of the section such that the void at the first end is partlycovered by the dummy gate and such that the void at the second end ispartly covered by the dummy gate, providing resist material within thevoid at the first end of the section and within the void at the secondend of the section, wherein the resist material is selected such that itoxidizes upon EUV exposure, exposing the wafer to EUV light therebyconverting the exposed resist material to an oxide wherein the unexposedresist material is under the dummy gate, selectively removing the dummygate and the unexposed resist material, forming a gate between thefunctional layers and between the exposed resist material at the firstend and the exposed resist material at the second end of the section,thus obtaining aligned gates for the functional layers wherein thefunctional layers are corresponding with the nanowires or nanosheets. 2.The method according to claim 1, wherein the provided resist material ishydrogen silsesquioxane.
 3. The method according to claim 1, wherein theresist material is applied by spin coating.
 4. The method according toclaim 1, wherein the at least partly removing of the stack ofsacrificial layers is done such that a pillar of the stack ofsacrificial layers is remaining wherein a width of this pillar isshorter than a predefined gate length.
 5. The method according to claim1, wherein forming the gate comprises: depositing gate dielectricmaterial around the nanowires or nanosheets, depositing gate materialaround the gate dielectric material thereby forming the gate.
 6. Themethod according to claim 1, wherein at least partly removing the stackof sacrificial layers to form the void is done by isotropic etching. 7.The method according to claim 1, the method comprising a step wherein asource is formed at one side of a nanowire material next to the dummygate or gate and a drain is formed at an opposite end of the nanowirematerial at the opposite side of the dummy gate or gate.
 8. The methodaccording to claim 1, the method comprising an implant anneal step onlyafter removing the unexposed resist material.
 9. The method according toclaim 1, wherein providing the wafer comprises depositing a stack oflayers on a substrate, the stack of layers comprising alternatingsacrificial and functional layers and forming at least one fin in thestack of layers.
 10. The method according to claim 9, wherein thedepositing of the stack of layers comprises depositing at least twofunctional layers.
 11. The method according to claim 10, wherein thedepositing of the stack of layers comprises depositing at least threefunctional layers.
 12. The method according to claim 9, wherein thedepositing of the stack of layers comprises depositing functional layerswhich are comprising Silicon, or SiGe, or Ge, or InGaAs, or III-Vmaterial.
 13. The method according to claim 12, wherein the depositingof the stack of layers comprises depositing functional layers which arecomprising Ge and sacrificial layers which are comprising SiGe.
 14. Themethod according to claim 12, wherein the depositing of the stack oflayers comprises depositing functional layers which are comprising Siand sacrificial layers which are comprising SiGe.